# Accelerators

* [Learning resources](#learning-resources)
* [Accelerator Design](#accelerator-design)
  * [Languages](#languages)
  * [Tools](#tools)
  * [Techniques](#techniques)

## Learning resources

* [Tutorial on Hardware Accelerators for Deep Neural Networks](http://eyeriss.mit.edu/tutorial.html)

## Accelerator Design

* [Languages, Tools, and Techniques for Accelerator Design, ACM SIGARCH](https://www.sigarch.org/languages-tools-and-techniques-for-accelerator-design/)
* [Productive Parallel Programming for FPGA with HLS](https://spcl.inf.ethz.ch/Teaching/hls-tutorial/) - ETH Parallel Computing lab

### Languages

* [Dahlia](https://capra.cs.cornell.edu/dahlia/) - A programming language for generating FPGA Predictable Accelerator Design designs. It uses affine types to reason about memory use and drastically reduces the parameter space of architectural parameters while accepting Pareto-optimal designs
* [Aetherling](https://aetherling.org/) - A system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits.

### Tools

### Techniques

* [Accelergy](http://accelergy.mit.edu/) - An Architecture-Level Energy Estimation Methodology for Accelerator Designs


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