Constraining Designs for Synthesis and Timing Analysis | A Practical Guide to Synopsys Design Constraints (SDC) - Gangadharan, Sridhar, Churiwala, Sanjay.
Static Timing Analysis for Nanometer Designs: A Practical Approach - Jayaram Bhasker and Rakesh Chadha.
FuseSoC - FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code. Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.
EDAlize - An abstraction library for interfacing EDA tools
Renode - Open source software development framework with commercial support from Antmicro that lets you develop, debug and test multi-node device systems reliably, scalably and effectively.
eFabless - Developer/Partner community that is also part of the Google Open Shuttle Program
FOSSi Foundation - Free and Open Source Silicon (FOSSi) are components and systems that are inside silicon devices (‘chips’). It is our core belief that building blocks that form such digital devices can be made free and open