Processors
Everything about processors
Open-source digital design implementations of Processors
ZipCPU - A small, light weight, RISC CPU soft core
Microwatt - A tiny Open POWER ISA softcore written in VHDL for FPGAs
OpenPiton - OpenPiton is an open source, general purpose, multithreaded manycore processor. It is a 64-bit architecture using SPARC v9 ISA with a distributed directory-based cache coherence protocol across on-chip networks
RISCV based
PicoRV32 - A Size-Optimized RISC-V CPU
Vectorblox ORCA - ORCA is an implementation of RISC-V. It is intended to target FPGAs and can be configured as either RV32I a RV32IM core.
Pulpino - PULPino is an open-source single-core microcontroller system, based on 32-bit RISC-V cores developed at ETH Zurich. PULPino is configurable to use either the RISCY or the zero-riscy core.
Icicle - Icicle is a 32-bit RISC-V system on chip for iCE40 HX8K, iCE40 UP5K and ECP5 FPGAs. It can be built with the open-source SymbiFlow toolchain and currently targets several development boards.
RISCV-BOOM - The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language.
Piccolo - Open-source RISC-V CPUs from Bluespec
RI5CY - RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
VexRiscv - FPGA-friendly RISC-V implementation written in SpinalHDL
darkriscv - opensouce RISC-V implemented from scratch in one night!
Ariane - Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions
Minerva - Minerva is a CPU core that currently implements the RISC-V RV32IM instruction set. Its microarchitecture is described in plain Python code using the nMigen toolbox.
BlackParrot - BlackParrot aims to be the default Linux-capable, cache-coherent, RV64GC multicore used by the world.
PulseRain Reindeer - RISCV RV32I[M] Soft CPU
Sodor - Educational microarchitectures collection for risc-v isa
BOOM - The Berkeley Out-of-Order RISC-V Processor.
RSD - RISC-V Out-of-Order Superscalar Processor
BRISC-V Explorer - Generate RISC V Cores for different configurations
RISCV Assembly visualizer - Visualize instruction flow through registers
Microarchitecture
Microarch cheatsheet - Centralised information about CPU μarch design such as caches, buffers, instruction width, etc
ISA
Interesting resources
sandsifter - The sandsifter audits x86 processors for hidden instructions and hardware bugs, by systematically generating machine code to search through a processor's instruction set, and monitoring execution for anomalies.
The MultiCore Association - To define and promote open specifications to enable multicore product development.
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