gem5 - The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.
Lapidary - Tool to enable more efficient gem5 simulations
CPULator - CPUlator Computer System Simulator designed as a tool for learning assembly-language programming and computer organization
ESESC - A fast multiprocessor simulator with detailed power, thermal, and performance models for modern out-of-order multicores.
Multi2Sim - Multi2Sim is a heterogeneous system simulator of CPUs and GPUs, used to test and validate new hardware designs before they are physically manufactured.
SniperSim - A multi-core, parallel, high-speed and accurate x86 simulator.
ZSim - zsim is a fast x86-64 simulator with a focus on simulating memory hierarchies and large, heterogeneous systems
MacSim - A heterogeneous architecture timing model simulator.
CACTI - An analytical tool that takes a set of cache/memory parameters as input and calculates its access time, power, cycle time, and area.
WATTCH - Architectural simulator that estimates CPU power consumption. Example
HotSpot - An accurate and fast thermal model suitable for use in architectural studies.
SESC - SuperScalar simulator is a cycle accurate architectural simulator that models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation.
Full-system simulators and their popularity in conferences (table from 2015)
Accel-Sim - Simulation framework for simulating and validating programmable accelerators like GPUs
GPGPU Sim - GPGPU-Sim provides a detailed simulation model of a contemporary GPUs
FireSim - FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs
MPGPUSim - MGPUSim is a Go based AMD GCN3 GPU simulator based-on the Akita framework.
SCALESim - SCALE sim is a CNN accelerator simulator, that provides cycle-accurate timing, power/energy, memory bandwidth and trace results for a specified accelerator configuration and neural network architecture.
STONNE - Simulation TOol of Neural Network Engines, a cycle-level, highly-modular and highly-extensible simulation framework that can plug into any high-level DNN framework as an accelerator device and perform end-to-end evaluation of flexible accelerator microarchitectures with sparsity support, running complete DNN models.
1.1.3. Micro-architecture/ISA simulators
ChampSim - ChampSim is a trace-based simulator for a microarchitecture study.
Mastik - A Micro-Architectural Side-Channel Toolkit
Venus - Venus is a RISC-V instruction set simulator built for education.
Ripes - Ripes is a visual computer architecture simulator and assembly code editor built for the RISC-V ISA.
WinMIPS64 - WinMIPS64 is an instruction set simulator, and is designed as a replacement for the popular Microsoft Windows utility WinDLX
Whisper - RISCV instruction set simulator (ISS) developed for the verification of the Swerv micro-controller. It allows the user to run RISCV code without RISCV hardware.
ARM Consistency Memory Model - The herd tool allows the user to execute the model with a specific question about the possible final states of the program using ARM consistency memory model.
MQSim - A Simulator for Modern NVMe and SATA SSDs
VAMPIRE - Variation-Aware model of Memory Power Informed by Real Experiments is an open-source DRAM power model based on an extensive experimental characterization of the power consumption of real DRAM modules.
RAMulator - Ramulator is a fast and cycle-accurate DRAM simulator [1] that supports a wide array of commercial, as well as academic, DRAM standards
Verilator - Verilator is the fastest free Verilog HDL simulator, and outperforms most commercial simulators
Icarus Verilog - Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools.
PyRTL - A collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research.
myHDL - MyHDL turns Python into a hardware description and verification language
LLHD - is an intermediate representation for digital circuit descriptions, together with an accompanying simulator and SystemVerilog/VHDL compiler.
TerosHDL - It is a open source IDE to make FPGA development easier
OpenLane - Automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
DREAMPlace - Deep learning toolkit-enabled VLSI placement
1.2.1. Digital/Analog Simulators
DigitalJS - Visualize and simulate digital logic using HDL
Digital - Digital is a easy-to-use digital logic designer and circuit simulator designed for educational purposes.
Xyce - open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.
Micro Cap 12 - Micro-Cap 12 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Now Open Source.
Logisim - Logisim is an educational tool for designing and simulating digital logic circuits.
LogisimITA - An independently developed fork of logisim that's preferred by many
Logisim-Evolution - Another flavour of Logisim after the development of original version was stopped
Antares - Digital Circuit Learning Platform. A free, powerful platform for designing, simulating and explaining digital circuits
Data sheet scrubber - The FASoC Datasheet Scrubber is a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information.
HDL Checker - HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up.
RgGen - RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR)
System RDL Compiler - The systemrdl-compiler module implements a generic compiler front-end for Accellera's SystemRDL 2.0 register description language.
Verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
svinst - This tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations. It uses sv-parser and is adapted from svlint.
Scastie - Playground for Chisel 3: A Modern Hardware Design Language
vcdMaker - Open application for translating text log files into the VCD (Variable Change Dump) format files. It is supposed to help you to debug your applications and systems