Tools and Utilities
Last updated
Was this helpful?
Last updated
Was this helpful?
- A tool for running small microbenchmarks on recent Intel and AMD x86 CPUs using hardware performance coutners.
- This tool allows automatic analysis of loop kernels using the Execution Cache Memory (ECM) model, the Roofline model and actual benchmarks. kerncraft provides a framework to investigate the data reuse and cache requirements by static code analysis. In combination with the Intel IACA tool kerncraft can give a good overview of both in-core and memory bottlenecks and use that data to apply performance models.
- A portable profiling and tracing toolkit for performance analysis of parallel programs written in Fortran, C, C++, UPC, Java, Python.
- A high-performance CPU, GPU and memory profiler for Python
- WhyProfiler is a CPU profiler for Jupyter notebook that not only identifies hotspots but can suggest faster alternatives.
- Estimate the cost of running deep learning workloads on cloud GPUs
- Up-to-date information on the features and pricing of GPU cloud providers.
- Hardware-assisted CPU profiling mechanism that offers detailed profiling capabilities.
- Cachegrind is a high-precision tracing profiler. It runs slowly, but collects precise and reproducible profiling data. Cachegrind can also simulate how your program interacts with a machine's cache hierarchy and branch predictor.
- measure memory latencies and b/w, and how they change with increasing load on the system
- Curious Coding's walkthrough on pointer chasing and other memory optimizations
- Pointer chase to reveal memory bandwidth and loaded-latency
- Repository of communication and compute micro-benchmarks as well as full workloads for evaluating training and inference platforms
- Warehouse scale traces captured using DynamoRIO's drmemtrace. The traces are records of instruction and memory accesses as described at Trace Format
- Consistent measurements of accuracy, speed, and efficiency on hardware for ML workloads
- Task-Parallel PARSEC
- Chai is a benchmark suite of Collaborative Heterogeneous Applications for Integrated-architectures. The Chai benchmarks are designed to use the latest features of heterogeneous architectures such as shared virtual memory and system-wide atomics to achieve efficient simultaneous collaboration between host and accelerator devices.
- MachSuite is a benchmark suite intended for accelerator-centric research.
- Distributed Deep Learning Training simulator, developed in collaboration between Georgia Tech, Meta and Intel.
- Structural Simulation Toolkit - Using the supercomputers of today to build the supercomputers of tomorrow
- The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.
- Tool to enable more efficient gem5 simulations
- Documentation on SLICC
- CPUlator Computer System Simulator designed as a tool for learning assembly-language programming and computer organization
- A fast multiprocessor simulator with detailed power, thermal, and performance models for modern out-of-order multicores.
- Multi2Sim is a heterogeneous system simulator of CPUs and GPUs, used to test and validate new hardware designs before they are physically manufactured.
- A multi-core, parallel, high-speed and accurate x86 simulator.
- zsim is a fast x86-64 simulator with a focus on simulating memory hierarchies and large, heterogeneous systems
- A heterogeneous architecture timing model simulator.
- An analytical tool that takes a set of cache/memory parameters as input and calculates its access time, power, cycle time, and area.
- Architectural simulator that estimates CPU power consumption.
- An accurate and fast thermal model suitable for use in architectural studies.
- SuperScalar simulator is a cycle accurate architectural simulator that models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation.
Full-system simulators and their popularity in conferences (table from 2015)
- Simulation framework for simulating and validating programmable accelerators like GPUs
- GPGPU-Sim provides a detailed simulation model of a contemporary GPUs
- FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs
- MGPUSim is a Go based AMD GCN3 GPU simulator based-on the Akita framework.
- SCALE sim is a CNN accelerator simulator, that provides cycle-accurate timing, power/energy, memory bandwidth and trace results for a specified accelerator configuration and neural network architecture.
- Simulation TOol of Neural Network Engines, a cycle-level, highly-modular and highly-extensible simulation framework that can plug into any high-level DNN framework as an accelerator device and perform end-to-end evaluation of flexible accelerator microarchitectures with sparsity support, running complete DNN models.
- ChampSim is a trace-based simulator for a microarchitecture study.
- A Micro-Architectural Side-Channel Toolkit
- Venus is a RISC-V instruction set simulator built for education.
- Ripes is a visual computer architecture simulator and assembly code editor built for the RISC-V ISA.
- WinMIPS64 is an instruction set simulator, and is designed as a replacement for the popular Microsoft Windows utility WinDLX
- RISCV instruction set simulator (ISS) developed for the verification of the Swerv micro-controller. It allows the user to run RISCV code without RISCV hardware.
- Break down x86 SIMD instructions
- Accurately simulate the caching (allocation/hit/miss/replace/evict) behavior of all cache levels found in modern processors
- A validated NVRAM simulator
- A Low-level NVRAM Profiler
- An Architectural Level Main Memory Simulator for Emerging Non-Volatile Memories
- A simple trace-based cache simulator
- A cycle accurate DRAM simulator
- The herd tool allows the user to execute the model with a specific question about the possible final states of the program using ARM consistency memory model.
- A Simulator for Modern NVMe and SATA SSDs
- Variation-Aware model of Memory Power Informed by Real Experiments is an open-source DRAM power model based on an extensive experimental characterization of the power consumption of real DRAM modules.
- Ramulator is a fast and cycle-accurate DRAM simulator [1] that supports a wide array of commercial, as well as academic, DRAM standards
- Animations to illustrate cache behavior
- A cycle-accurate interconnection network simulator
- Dependency-Tracking Trace-Based Network-on-Chip Simulation.
- Network-on-Chip Simulator
- A Simulator for NoC Interconnect Routing and Application Modeling
- Verilator is the fastest free Verilog HDL simulator, and outperforms most commercial simulators
- Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools.
- Open source FPGA tooling available under
- GTKWave is a fully featured GTK+ based wave viewer.
- WaveDrom draws your Timing Diagram or Waveform from simple textual description.
- Front-end for Yosys-based formal verification flows
- Formal tools for OSH
- Yosys is a framework for Verilog RTL synthesis.
- A High-Performance Timing Analysis Tool for VLSI Systems
- Fast IC layout and schematic editor capable of reading and writing common EDA formats
- An static random access memory (SRAM) compiler.
- A suite of tools including Qflow covering various aspects of digital design
- the VLSI layout editor, extraction, and DRC tool.
- the circuit drawing and schematic capture tool.
- the switch-level digital circuit simulator.
- the circuit netlist comparison (LVS) and netlist conversion tool.
- the over-the-cell (sea-of-gates) detail router.
- a complete digital synthesis design flow using open-source software and open-source standard cell libraries.
- the printed circuit board layout editor.
- open source spice simulator
- open source mixed-signal simulator supporting Spice and Verilog syntax, also see
- Includes , , , , and other tools.
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
- A powerful, innovative and intuitive EDA tool for everyone!
- Asynchronous Circuit Design Toolkit to support the design and implementation of asynchronous logic
- PyMTL is an open-source, Python-based framework for multi-level hardware modeling.
- FPGA IP generator supporting highly-customizable homogeneous FPGA architectures
- This library contains various SystemC/TLM-2.0 modules that enable co-simulation of Xilinx QEMU, SystemC/TLM-2.0 models and RTL.
- focused on developing a complete system-on-chip (SoC) synthesis tool from user specification to GDSII.
- Edalize is a Python Library for interacting with EDA tools.
- A refreshed Python toolbox for building complex digital hardware
- Just-in-time compiler for Verilog
- A collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research.
- MyHDL turns Python into a hardware description and verification language
- is an intermediate representation for digital circuit descriptions, together with an accompanying simulator and SystemVerilog/VHDL compiler.
- It is a open source IDE to make FPGA development easier
- Automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
- Deep learning toolkit-enabled VLSI placement
- A modular build system for hardware ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".
- Visualize and simulate digital logic using HDL
- Digital is a easy-to-use digital logic designer and circuit simulator designed for educational purposes.
- Run HDL/HVL code in your browser
- Falstad circuit simulator
- Assembly Practice
- Verilog Practice
- Verilog to waves instantly
- Logic simulator in your browser
-
- open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.
- Micro-Cap 12 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Now Open Source.
- Logisim is an educational tool for designing and simulating digital logic circuits.
- An independently developed fork of logisim that's preferred by many
- Another flavour of Logisim after the development of original version was stopped
- Digital Circuit Learning Platform. A free, powerful platform for designing, simulating and explaining digital circuits
- In-browser Verilog design environment
- TinyEMU is a system emulator for the RISC-V and x86 architectures.
- Unicorn is a lightweight multi-platform, multi-architecture CPU emulator framework.
- A toolbox of 8-bit chip-emulators, helper code and complete embeddable system emulators
- Very simple Von Neumann Architecture Computer. Similar
- a command line debugger that focuses on visualizing how software changes memory. It's able to emulate statically linked i8086 and x86_64-pc-linux-gnu programs
- The FASoC Datasheet Scrubber is a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information.
- SVUT is a very simple flow to create a Verilog/SystemVerilog unit test.
- Create register maps and headers
- Visually dissect and analyze bit strings.
- BitField diagram Renderer
- Provides dot visualizations of chisel/firrtl circuites
- Handy for getting from simulation to spec quickly.
- Python-based IP-XACT parser
- SystemVerilog to Verilog conversion
- System Verilog lint using rust
- HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up.
- README embeddable waveforms!
- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR)
- The systemrdl-compiler module implements a generic compiler front-end for Accellera's SystemRDL 2.0 register description language.
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
- Useful tools for working with HDL
- Altera Quartus/ Icestorm report parser
- Editable examples of registers
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
- This tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations. It uses sv-parser and is adapted from svlint.
- A command-line hex viewer
- Playground for Chisel 3: A Modern Hardware Design Language
- Open application for translating text log files into the VCD (Variable Change Dump) format files. It is supposed to help you to debug your applications and systems
- A Hex Editor for Reverse Engineers, Programmers
