Tools, Utilities, Simulators, Emulators and more

1. Tools

Performance Analysis

  • CacheGrind - Cachegrind is a high-precision tracing profiler. It runs slowly, but collects precise and reproducible profiling data. Cachegrind can also simulate how your program interacts with a machine's cache hierarchy and branch predictor.

  • nanoBench - A tool for running small microbenchmarks on recent Intel and AMD x86 CPUs using hardware performance coutners. Github

  • kerncraft - This tool allows automatic analysis of loop kernels using the Execution Cache Memory (ECM) model, the Roofline model and actual benchmarks. kerncraft provides a framework to investigate the data reuse and cache requirements by static code analysis. In combination with the Intel IACA tool kerncraft can give a good overview of both in-core and memory bottlenecks and use that data to apply performance models.

  • TAU Performance System - A portable profiling and tracing toolkit for performance analysis of parallel programs written in Fortran, C, C++, UPC, Java, Python.

  • Scalene - A high-performance CPU, GPU and memory profiler for Python

  • WhyProfiler - WhyProfiler is a CPU profiler for Jupyter notebook that not only identifies hotspots but can suggest faster alternatives.

Benchmarking/Profiling

  • PARAM - Repository of communication and compute micro-benchmarks as well as full workloads for evaluating training and inference platforms

  • Google Workload Traces - Warehouse scale traces captured using DynamoRIO's drmemtrace. The traces are records of instruction and memory accesses as described at Trace Format

  • MLPerf - Consistent measurements of accuracy, speed, and efficiency on hardware for ML workloads

  • tp-parsec - Task-Parallel PARSEC

  • CHAI - Chai is a benchmark suite of Collaborative Heterogeneous Applications for Integrated-architectures. The Chai benchmarks are designed to use the latest features of heterogeneous architectures such as shared virtual memory and system-wide atomics to achieve efficient simultaneous collaboration between host and accelerator devices.

  • MachSuite - MachSuite is a benchmark suite intended for accelerator-centric research.

1.1. Simulators

System

  • ASTRA-Sim - Distributed Deep Learning Training simulator, developed in collaboration between Georgia Tech, Meta and Intel.

  • SST - Structural Simulation Toolkit - Using the supercomputers of today to build the supercomputers of tomorrow

1.1.1. Architectural

  • gem5 - The gem5 simulator is a modular platform for computer-system architecture research, encompassing system-level architecture as well as processor microarchitecture.

  • CPULator - CPUlator Computer System Simulator designed as a tool for learning assembly-language programming and computer organization

  • ESESC - A fast multiprocessor simulator with detailed power, thermal, and performance models for modern out-of-order multicores.

  • Multi2Sim - Multi2Sim is a heterogeneous system simulator of CPUs and GPUs, used to test and validate new hardware designs before they are physically manufactured.

  • SniperSim - A multi-core, parallel, high-speed and accurate x86 simulator.

  • ZSim - zsim is a fast x86-64 simulator with a focus on simulating memory hierarchies and large, heterogeneous systems

  • MacSim - A heterogeneous architecture timing model simulator.

  • CACTI - An analytical tool that takes a set of cache/memory parameters as input and calculates its access time, power, cycle time, and area.

  • WATTCH - Architectural simulator that estimates CPU power consumption. Example

  • HotSpot - An accurate and fast thermal model suitable for use in architectural studies.

  • SESC - SuperScalar simulator is a cycle accurate architectural simulator that models a very wide set of architectures: single processors, CMPs, PIMs, and thread level speculation.

1.1.2. Hardware Accelerator (incl. GPU) simulators

  • Accel-Sim - Simulation framework for simulating and validating programmable accelerators like GPUs

  • GPGPU Sim - GPGPU-Sim provides a detailed simulation model of a contemporary GPUs

  • FireSim - FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs

  • MPGPUSim - MGPUSim is a Go based AMD GCN3 GPU simulator based-on the Akita framework.

  • SCALESim - SCALE sim is a CNN accelerator simulator, that provides cycle-accurate timing, power/energy, memory bandwidth and trace results for a specified accelerator configuration and neural network architecture.

  • STONNE - Simulation TOol of Neural Network Engines, a cycle-level, highly-modular and highly-extensible simulation framework that can plug into any high-level DNN framework as an accelerator device and perform end-to-end evaluation of flexible accelerator microarchitectures with sparsity support, running complete DNN models.

1.1.3. Micro-architecture/ISA simulators

  • ChampSim - ChampSim is a trace-based simulator for a microarchitecture study.

  • Mastik - A Micro-Architectural Side-Channel Toolkit

  • Venus - Venus is a RISC-V instruction set simulator built for education.

  • Ripes - Ripes is a visual computer architecture simulator and assembly code editor built for the RISC-V ISA.

  • WinMIPS64 - WinMIPS64 is an instruction set simulator, and is designed as a replacement for the popular Microsoft Windows utility WinDLX

  • Whisper - RISCV instruction set simulator (ISS) developed for the verification of the Swerv micro-controller. It allows the user to run RISCV code without RISCV hardware.

  • SIMD Giraffe - Break down x86 SIMD instructions

1.1.4. Memory Simulators

  • PyCacheSim - Accurately simulate the caching (allocation/hit/miss/replace/evict) behavior of all cache levels found in modern processors

  • VANS - A validated NVRAM simulator

  • LENS - A Low-level NVRAM Profiler

  • NVMain - An Architectural Level Main Memory Simulator for Emerging Non-Volatile Memories

  • Cache simulator - A simple trace-based cache simulator

  • DRAMSim2 - A cycle accurate DRAM simulator

  • ARM Consistency Memory Model - The herd tool allows the user to execute the model with a specific question about the possible final states of the program using ARM consistency memory model.

  • MQSim - A Simulator for Modern NVMe and SATA SSDs

  • VAMPIRE - Variation-Aware model of Memory Power Informed by Real Experiments is an open-source DRAM power model based on an extensive experimental characterization of the power consumption of real DRAM modules.

  • RAMulator - Ramulator is a fast and cycle-accurate DRAM simulator [1] that supports a wide array of commercial, as well as academic, DRAM standards

  • Intel TSX MESI Cache simulator - Animations to illustrate cache behavior

1.1.5. Interconnect Simulators

  • BookSim - A cycle-accurate interconnection network simulator

  • NetTrace - Dependency-Tracking Trace-Based Network-on-Chip Simulation. Source code

  • Noxim - Network-on-Chip Simulator

  • NIRGAM - A Simulator for NoC Interconnect Routing and Application Modeling

1.2. Open Source Tools for Digital Design

  • Verilator - Verilator is the fastest free Verilog HDL simulator, and outperforms most commercial simulators

  • Icarus Verilog - Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools.

  • SymbiFlow - Open source FPGA tooling available under YosysHQ

  • GTKWave - GTKWave is a fully featured GTK+ based wave viewer.

  • Wavedrom - WaveDrom draws your Timing Diagram or Waveform from simple textual description.

  • SymbiYosys - Front-end for Yosys-based formal verification flows

  • Upscale Project - Formal tools for OSH

  • Yosys - Yosys is a framework for Verilog RTL synthesis.

  • Open Timer - A High-Performance Timing Analysis Tool for VLSI Systems

  • Glade - Fast IC layout and schematic editor capable of reading and writing common EDA formats

  • OpenRAM - An open-source static random access memory (SRAM) compiler.

  • Open Circuit Design Flow - A suite of tools including Qflow covering various aspects of digital design

    • Magic - the VLSI layout editor, extraction, and DRC tool.

    • XCircuit - the circuit drawing and schematic capture tool.

    • IRSIM - the switch-level digital circuit simulator.

    • Netgen - the circuit netlist comparison (LVS) and netlist conversion tool.

    • Qrouter - the over-the-cell (sea-of-gates) detail router.

    • Qflow - a complete digital synthesis design flow using open-source software and open-source standard cell libraries.

    • PCB - the printed circuit board layout editor.

  • ngspice - open source spice simulator

  • gnucap - open source mixed-signal simulator supporting Spice and Verilog syntax, also see GnuCap GitBook

  • Open Register Design - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

  • LibrePCB - A powerful, innovative and intuitive EDA tool for everyone!

  • ACT Tools Suite - Asynchronous Circuit Design Toolkit to support the design and implementation of asynchronous logic

  • PyMTL - PyMTL is an open-source, Python-based framework for multi-level hardware modeling.

  • OpenFPGA - FPGA IP generator supporting highly-customizable homogeneous FPGA architectures

  • LibSystemCTLM - This library contains various SystemC/TLM-2.0 modules that enable co-simulation of Xilinx QEMU, SystemC/TLM-2.0 models and RTL.

  • Fully autonomous SoC Synthesis - focused on developing a complete system-on-chip (SoC) synthesis tool from user specification to GDSII.

  • EDALIZE - Edalize is a Python Library for interacting with EDA tools.

  • nMigen - A refreshed Python toolbox for building complex digital hardware

  • Cascade - Just-in-time compiler for Verilog

  • PyRTL - A collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research.

  • myHDL - MyHDL turns Python into a hardware description and verification language

  • LLHD - is an intermediate representation for digital circuit descriptions, together with an accompanying simulator and SystemVerilog/VHDL compiler.

  • TerosHDL - It is a open source IDE to make FPGA development easier

  • OpenLane - Automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

  • DREAMPlace - Deep learning toolkit-enabled VLSI placement

  • SiliconCompiler - A modular build system for hardware ("make for silicon"). The project philosophy is to "make the complex possible while keeping the simple simple".

1.2.1. Digital/Analog Simulators

  • DigitalJS - Visualize and simulate digital logic using HDL

  • Digital - Digital is a easy-to-use digital logic designer and circuit simulator designed for educational purposes.

  • EDA Playground - Run HDL/HVL code in your browser

  • Electronic Circuit Simulator - Falstad circuit simulator

  • ASMBits - Assembly Practice

  • HDLBits - Verilog Practice

  • 8bit Workshop - Verilog to waves instantly

  • LogicEmu - Logic simulator in your browser

  • Xyce - open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by supporting large-scale parallel computing platforms.

  • Micro Cap 12 - Micro-Cap 12 is an integrated schematic editor and mixed analog/digital simulator that provides an interactive sketch and simulate environment for electronics engineers. Now Open Source.

  • Logisim - Logisim is an educational tool for designing and simulating digital logic circuits.

  • LogisimITA - An independently developed fork of logisim that's preferred by many

  • Logisim-Evolution - Another flavour of Logisim after the development of original version was stopped

  • Antares - Digital Circuit Learning Platform. A free, powerful platform for designing, simulating and explaining digital circuits

  • MakerChip - In-browser Verilog design environment

1.3. Emulators

  • TinyEMU - TinyEMU is a system emulator for the RISC-V and x86 architectures.

  • Unicorn - Unicorn is a lightweight multi-platform, multi-architecture CPU emulator framework.

  • 8bit Chip Emulator - A toolbox of 8-bit chip-emulators, helper code and complete embeddable system emulators

  • Little Man Computer - Very simple Von Neumann Architecture Computer. Similar RISC

  • Blinken Lights - a command line debugger that focuses on visualizing how software changes memory. It's able to emulate statically linked i8086 and x86_64-pc-linux-gnu programs

2. Utilities

2.1. Hardware Design

  • Data sheet scrubber - The FASoC Datasheet Scrubber is a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information.

  • SystemVerilog Unit Test (SVUT) - SVUT is a very simple flow to create a Verilog/SystemVerilog unit test.

  • AirHDL - Create register maps and headers

  • BitBench - Visually dissect and analyze bit strings.

  • Bitfield - BitField diagram Renderer

  • Diagrammer - Provides dot visualizations of chisel/firrtl circuites

  • VCD2Wavedrom - Handy for getting from simulation to spec quickly.

  • ipyxact - Python-based IP-XACT parser

  • sv2v - SystemVerilog to Verilog conversion

  • svlint - System Verilog lint using rust

  • HDL Checker - HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up.

  • Wavedrom to ASCII converter - README embeddable waveforms!

  • RgGen - RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR)

  • System RDL Compiler - The systemrdl-compiler module implements a generic compiler front-end for Accellera's SystemRDL 2.0 register description language.

  • Verismith - Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

  • Jeff's ASIC tools - Useful tools for working with HDL

  • Static Timing Analysis Diagram Renderer - Altera Quartus/ Icestorm report parser

  • Bitfield/Register representations - Editable examples of registers

  • Verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

  • svinst - This tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations. It uses sv-parser and is adapted from svlint.

3. Misc

  • Hexyl - A command-line hex viewer

  • Scastie - Playground for Chisel 3: A Modern Hardware Design Language

  • vcdMaker - Open application for translating text log files into the VCD (Variable Change Dump) format files. It is supposed to help you to debug your applications and systems

  • ImHex - A Hex Editor for Reverse Engineers, Programmers

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